Random Access Memories (RAM) are memories which temporarily store data in a memory array for use by other parts of an integrated circuit (IC), e.g. a microcontroller or microprocessor unit (MPU). In many ICs, the RAM is controlled by the MPU. For example, in an MPU-based IC used in smart card applications, the MPU controls the RAM to prevent misuse of data stored. If the MPU detects an abnormal condition (e.g., a frequency, temperature, or voltage which is too high or too low), the MPU forces the IC into a full reset to prevent a hacker from gaining access to the sensitive data stored in the chip. Upon forcing a reset, the entire contents of the RAM must be cleared or wiped in case some of the sensitive data was stored in RAM when the abnormal condition was detected.
FIG. 1 illustrates a typical RAM cell 10, while FIG. 2 shows a typical 256 byte (2048 bit) RAM array 30 organized in thirty-two rows by sixty-four columns. One known method for clearing the contents of the illustrated RAM array will be discussed in conjunction with these two figures. Cell 10 includes two cross-coupled inverters 12 and 14. Inverter 12 includes a P-MOS transistor 16 and an N-MOS transistor 18, while inverter 14 includes a P-MOS transistor 20 and an N-MOS transistor 22. Cell 10 also includes two select transistors (N-MOS transistors) 24 and 26 which are used to select the particular row of the array to be written to in a write operation or to be cleared when the row is to be cleared or wiped. Within array 30, there is a cell, like cell 10, for each bit of the array. Additionally, within the array are row decoders 32, sense amplifiers 34, cross-coupled P-MOS devices 36 (one pair for each column of the array, and shown as P-MOS transistors 27 and 28 of FIG. 1), and N-MOS RAMWIPE transistors 38-42 (again, one for each column of the array). All P-devices shown in FIGS. 1 and 2 (namely transistors 16, 20, 27, and 28) are resistive devices, meaning that their "on" resistivity is much higher than that of N-MOS transistors 24, 26, and 38-42. The resistive devices could even be replaced by high value resistors with the same effect.
To wipe the contents of the RAM array, a zero is written to each cell of the array by forcing a "0" on Node 1 (N1) which in turn will eventually bring a "1" at node 2 (N2). This is accomplished by forcing the array's "RAMWIPE" line high, which in turns forces each "DATA" line (column) low when "ROWSEL" goes high to force N1 low. In other words, the classical way to erase the array contents is to select all rows of the array at once, and force a "0" into all array cells at the same time. To achieve this, each of RAMWIPE transistors 38-42 must be sized so that each can overpower all thirty two of the column's cross-coupled inverters (e.g. overpower transistor 20 of inverter 14 of the cell in FIG. 1) and the column's cross coupled P-devices (e.g. by overpowering transistor 27 of the cell of FIG. 1). Such a transistor corresponds in size to a transistor thirty times bigger than the N-MOS transistors used to write a "0" or a "1" in RAM during a normal RAM write operation.
FIG. 3 illustrates a typical row decoder circuit 50 of row decoder 32 in more detail. Circuit 50 is used to select a row of the memory array, and is replicated for each row of the array. Circuit 50 includes a plurality of transistors 52-60 for providing an address select value of the array and an N-MOS transistor 62 coupled to the plurality of transistors 52-60 and to a Row-Select-Enable signal. Only when the correct value is present on transistors 52-60 will the Row-Select-Enable Signal go high (i.e. become enabled). Circuit 50 also includes a P-MOS transistor 64 coupled to the Row-Select-Enable signal and to the plurality of transistors 52-60 at a Node 3 (N3), an inverter 66 having N3 as an input and a ROWSEL (for Row Select) signal as an output, a P-MOS transistor 68 also coupled to N3 and gated by ROWSEL, and an N-MOS transistor 69 coupled to the input of inverter 66 and being gated by the RAMWIPE signal. When Row-Select Enable is high, transistor 64 is in its "off" state and N3 is pulled low, resulting in ROWSEL being asserted (as a result of inverter 66). When Row-Select Enable is low, transistor 64 is in its "on" state and N3 is pulled high, resulting in ROWSEL being negated. Transistor 68 is included to stabilize the value at N3, high or low, or in other words to prevent leakage which might otherwise affect assertion of ROWSEL. Transistor 69 is used to select the row to be cleared upon assertion of the RAMWIPE signal. In comparison, transistors 38-42 (shown in FIG. 2) are used to select their respective columns during assertion of the same signal.
A row is selected when N3 is pulled low (a logic level "0"), and thus ROWSEL goes high (is a logic level "1") due to inverter 66. In a normal read/write operation of the array, N3 is pulled low when the Row-Select Enable signal is high and the appropriate address value is present on the plurality of transistors 52-60. Different combinations of address values are used so that only one row is selected at a time during a normal read/write operation. But when one is clearing or wiping the entire RAM array, all rows of the array are selected at the same time by asserting the RAMWIPE signal such that N3 is pulled low for each row simultaneously. When RAMWIPE is asserted the address value at transistors 52-60 is ignored.
Again, the most significant disadvantage of the prior art circuitry described above for clearing or wiping the contents of a RAM array is the size of transistors 38-42 needed to adequately select all rows of the array at the same time. As with all integrated circuits, a primary goal is to minimize the size of the final die. Another disadvantage is that in order for transistors 38-42 to overpower the cross-coupled inverters in each cell of their respective columns and the cross-coupled P-devices at the top of the column, there is a very large current surge during a clear operation which can adversely affect other parts of the integrated circuit. Thus, there is a need for an improved circuit for clearing or wiping the contents of a RAM array which occupies a minimum amount of silicon die area and draws a much smaller amount of current during a clearing operation.